SoftGPU is a software GPU runtime for developers. The first integration target is AMD HIP. The host implementation is Rust. The point is not to replace an R9700. The point is to inspect execution, test assumptions, and eventually catch memory and synchronization mistakes with diagnostics another engineer can reproduce.
The series starts from a flaky kernel: it passes until you change the input size; logging makes the bug vanish; a driver change brings it back differently. Hardware remains essential for performance and agreement. Vendor sanitizers already exist. SoftGPU is for control over the execution environment — and for being honest about what a passing test has actually shown.
The integration boundary is ADR-0001: keep the official AMD compiler and HIP runtime; substitute at ROCr/HSA userspace. SoftGPU does not mock HIP as its compatibility path, and it does not start by emulating PCIe or firmware.
As of the repository’s 16 September 2026 snapshot (status, v0.8.0), SoftGPU can load as an HSA library, observe queues and AQL packets, inspect AMDGPU code-object metadata, run a disclosed functional IR, sanitize and debug that IR, and execute a named gfx1201 subset for a tiny registered kernel. Arbitrary hipcc binaries and hardware differential are not claimed.
The status document is the evidence ledger. If an article and the status file disagree, trust the status file.
Articles in this series
- Why We’re Building SoftGPU — A developer-oriented virtual GPU, built around a simple requirement: explain what happened, and be honest about what you know.
- SoftGPU: The GPU Stack from HIP to Silicon — Applications talk HIP. Silicon speaks packets and firmware. SoftGPU substitutes at ROCr/HSA so the real compiler and runtime stay in the path.
- SoftGPU: Impersonating a GPU Without Lying — Discovery APIs tempt emulators to invent CU counts and wave sizes. SoftGPU treats device identity as a contract with provenance.
- SoftGPU: HSA Queues and Signals — HIP eventually submits work through user-mode queues. SoftGPU proves observation, wraparound, and wait-cancel before it ever runs a kernel.
- SoftGPU: HSA/AQL Dispatch, Without Running the Kernel — A HIP launch ends as a 64-byte AQL packet. SoftGPU validates, traces, and diagnostically completes that packet — and still does not execute it.
- SoftGPU: Fat Binaries, ELF Notes, and gfx1201 — HIP ships device binaries, not source. SoftGPU reads AMDGPU metadata notes with a bounded parser — and still does not execute the ISA bytes.
- SoftGPU: Emulation Versus Simulation — People say GPU emulator when they mean four different things. SoftGPU names which kind of execution it is performing, or it will claim hardware fidelity it does not have.
- SoftGPU: Grids, Workgroups, Waves, and Barriers — Wave, warp, and subgroup mean different things on different vendors. SoftGPU defines a software semantic machine without pretending it is gfx1201 silicon.
- SoftGPU: Building GPU Sanitizers — Hardware hides memory and sync defects until a rare schedule hits them. SoftGPU detects a declared class of defects with workgroup, wave, and lane context.
- SoftGPU: Debugging a Machine Made of Lanes — A sanitizer finding is only useful if another engineer can reproduce it, stop at the responsible step, and inspect wave and lane state.
- SoftGPU: Decoding an AMD GPU ISA Responsibly — ISA tables are easy to invent and hard to defend. SoftGPU’s gfx1201 subset is sourced from llvm-mc goldens, traps unknown encodings, and still does not claim a full GPU.
- SoftGPU: The First gfx1201 Kernel — Dispatch to machine code to a memory result for tiny_add — a named gfx1201 subset, a SoftGPU calling convention, and still not unrestricted hipLaunchKernel.
- Why Rust for a Software GPU — and What Rust Cannot Prove — Rust is SoftGPU’s host language because ownership and explicit types fit an evidence system. It does not prove an HSA ABI, a GPU memory model, or an R9700.